This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
In modern circuit designs, memory circuits and related mechanisms save power by inhibiting flip-flops from switching logic states when inactive. With clock gating circuits, non-contributing flip-flops may be selectively inactivated. However, conventional clock gating circuits use tri-state inverters to provide three-state or tri-state logic functions that allow for an output port to assume a high impedance state in addition to a low logic level (logic 0 state) and a high logic level (logic 1 state) to thereby effectively remove the output from the circuitry. This allows multiple circuits to share a same output line. Unfortunately, a disadvantage is that tri-state inverter implementations typically use 4 transistors for each tri-state inverter, which causes an area penalty in the circuitry.